Introducing the First Generation quadric architecture.

We built this architecture to meet the demands of various workloads. From Neural Networks to Digital Signal Processing to Computer Vision to the State of the Art that you're developing today we've got you covered. Develop your algorithms once and deploy them on any device that has a quadric architecture instance.  When our architecture improves so will your algorithms.

quadric Architecture

We built a highly-scalable, highly-configurable architecture from the ground up to meet the demands of tomorrow's algorithms, today.

single instruction
multiple decode

Every cycle each core gets the same instruction. Based on dynamic data at runtime, each core can interpret that instruction differently.

broadcast bus

The broadcast bus transmits loop invariant data, such as weights and constants, to all Vortex Cores at once.

software controlled
static memories

Large local memories offer the developer space for large data structures. Multiple ports allow for simultaneous reading and writing to keep the vortex core array busy.

any edge
load store

Edge load-store units are static and completely software-controlled, allowing for deterministic kernel runtimes. Each edge has a load-store unit, unlocking novel software API possibilities such as native data rotations and data remapping.

quadric architecture
driven by code

Build it
with quadric.

The first-generation quadric architecture is the world’s most advanced edge processor architecture designed to power computationally-intensive Artificial Intelligence and High-Performance Computing applications. A hybrid data-flow + Von Neumann machine provides high-performance computing for various workloads, including, but not limited to, Neural Networks, Computer Vision, Digital Signal Processing, BLAS, and more. We achieve this by:
a flat 2d representation of the main components of the first generation quadric architecture
Re-imagining data access to a massively parallel array of cores
Prioritizing spatial and temporal data locality without the use of caches
Providing large amounts of on-chip memory to reduce external traffic and provide large internal bandwidths significantly improving algorithm performance
Allowing for queued, asynchronous data transfer to/from DDR, decoupling data access from compute
up arrow
Scalable and Fully Digital.
Configure and instantiate the quadric architecture in your SOC. No matter the application, there is a configuration for your workload.
web chart going up
Driven by Code.
Simple yet powerful. The architecture is completely driven by code, giving the power to the developer to optimize algorithm performance.
vortex core monogram
Powered by Vortex Cores.
This architecture can handle anything you throw at it. Turing complete, scalable and powerful they can handle anything you throw at them.

powered by

Vortex Cores

Our compute engine is scalable, powerful, and general enough to handle any workload.

configurable multimode multiply accumulate

general-purpose arithmetic logic unit

scalable single-cycle local memory 

single-cycle data sharing

the right data.
right on time.

scalable to meet the needs of any workload

A depiction of scalability of the quadric architecture.
One Architecture Every Deployment
scalability to meet the demands of any application
  • q8 for embedded sensors
  • q16 for edge applications
  • q32 for larger embedded systems
  • q64 for server applications
Reach out to learn more.
Thank you! Your submission has been received!
Oops! Something went wrong while submitting the form.
Driven by Code

Our Architecture gives developer's the peace of mind to develop their algorithms

The architecture is instruction driven, leading to software manageability of hardware that keeps pace with the ever-changing demands of applications. Coupled with the architecture is a software programming model tailored for developer ease of use. The software programming model allows the developer to express graph-based and non-graph based algorithms in unison.
vortex core monogram


Our architecture is compatible with all kinds of algorithms. Master the architecture with source mode. Drive the architecture with the power of code.
A screenshot of a kernel written using the quadric SDK C++ API.
web chart going up


Using the quadric SDK, predict your algorithm performance on any quadric Architecture Instance. Or, use it as a tool to fine tune your own Architecture instance.
A powerful combination

Hardware + Software a powerful combination.

With the power of software, profile and fine tune your algorithm's performance. Deploy it on our architecture.